The invention relates generally to methods for monitoring and controlling processes employed in substrate processing. More specifically, the invention relates to techniques for controlling photoresist etching in the fabrication of integrated circuit devices.
The processing of a semiconductor substrate (such as a wafer or a glass panel) often involves the etching of the overlaying photoresist layer. For example, in a process known as dual damascene, it is desirable to etch back the photoresist layer prior to a given trench etch. To facilitate understanding, the dual damascene process will be employed as an example throughout this disclosure. It should be kept in mind, however, that the invention herein applies to any process in which control of the photoresist etch step is desired.
Generally speaking, dual-damascene integration may be used to form high-speed wiring interconnects in complex integrated circuit devices. In dual-damascene integration, trenches and vias are formed in a low-permittivity (low-κ) dielectric, such as a fluorosilicate glass (FSG), an organosilicate glass (OSG), e.g., BLACK DIAMOND or CORAL, or a spin-on organic (SOG), e.g., SILK or FLARE, and filled with a low-resistance metal, usually copper. The copper is used to reduce the resistance of the metal interconnects, and the low-κ dielectric is used to reduce the parasitic capacitance between the metal interconnects.
A via-first dual-damascene process sequence is illustrated in FIGS. 1A–1F. In FIG. 1A, a dual-damascene stack 100 is formed on a copper line 102. In general, a dual damascene stack is made of a sequence of hard masks and interlayer dielectrics. For example, the dual damascene stack 100 includes a top hard mask 104, an embedded hard mask 106, and a bottom hard mask 108. The dual damascene stack 100 also includes low-κ interlayer dielectrics 110, 112. The top hard mask 104 protects the interlayer dielectric 110 from chemicals used in photoresist stripping and may be omitted depending on the low-κ material used in the interlayer dielectric 110. The embedded hard mask 106 may act as an etch stop layer. The bottom hard mask 108 prevents the copper 102 from diffusing into the interlayer dielectric 112.
In FIG. 1B, a photoresist mask 114 having a via pattern is applied on the stack 100. A via 116 is formed in the stack 100 by etching the via mask 114 through the top hard mask 104, the interlayer dielectric 110, the embedded hard mask 106, and the interlayer dielectric 112, stopping on the bottom hard mask 108. In FIG. 1C, the photoresist mask (114 in FIG. 1B) is stripped off and replaced with a photoresist mask 118 having a trench pattern. A trench 120 is formed in the stack 100 by etching the trench mask 118 through the top hard mask 104 and the interlayer dielectric 110, stopping on the embedded hard mask 106. In FIG. 1D, the trench mask (118 in FIG. 1C) is stripped off, and copper 122 is deposited into the via 116 and trench 120 and polished back to the surface of the trench 120. The via 116 and trench 120 are typically lined with a material such as tantalum to prevent copper from diffusing into the interlayer dielectrics 110, 112.
Prior to etching the trench 120, a plug is formed in the via 116 to protect the via 116 and the bottom hard mask 108 during etching of the trench 120 and to control the trench etch profile. Typically, the plug is made of a photoresist. The plug is formed by depositing a photoresist inside the via 116 and on the top hard mask 104 and etching back the photoresist. FIG. 1E shows photoresist 124 deposited inside the via 116 and on the top hard mask 104. Currently, a two-stage process is used for the photoresist etch back. In the first stage, a bulk etch process is used to planarize the blanket of photoresist 124 on the top hard mask 104. All of the photoresist 124 on the top hard mask 104 may be removed by the bulk etch process. More preferably, only a portion of the photoresist 124 on top of hard mask 104 is removed by the bulk etch process, down to a desired photoresist thickness before the recess etch step in the second stage.
In the second stage, a recess etch process is used to reduce the height of the column of photoresist 124 in the via 116 to form a plug having a specified height. FIG. 1F shows a plug 126 formed in the via 116 by performing the photoresist etch back.
Typically, the bulk etch is performed using by timed etch. Depending on the incoming thickness variation of the photoresist 124 from one wafer to another, the thickness of photoresist 124 remaining on the top hard mask 104 after the bulk etch process is terminated may vary substantially. Consequently, the total recess etch time may also vary substantially.
In comparison to the bulk etch process, the recess etch process is a slower process. Generally speaking, the recess etch is end-pointed using OES, and there may be an over-etch of, for example, 10 seconds to ensure that the photoresist clears. The slower process is required for better control of etching inside the via 116.
In general, the thicker the amount of photoresist 124 remaining on the stack 100, the longer the total recess etch time, resulting to decreased throughput. Using a timed etch process, there is also the possibility of the bulk etch front moving inside the via 116. This is undesirable because the bulk etch process is fast and aggressive and difficult to control inside the via 116.
From the foregoing, there is desired a method of controlling the photoresist etch back process such that total recess etch time is minimized regardless of incoming material variations. There is also desired a method of ensuring that the bulk etch front does not move inside the via.